Following manufacture, it is common practice to subject a printed circuit to testing appropriate toward ensuring that the resulting article has been correctly manufactured and is effectively operating within its specified parameters. One such test involves the capacitive measurement of printed circuit products to determine whether or not elements of the printed circuit (e.g., the networks, or nets, of the printed circuit) are open or shorted.
In general, this process involves measuring the capacitance of a circuit element relative to either an external reference plane or an internal power plane, and comparing the measured value to a previously determined (i.e., learned) "ideal" value. If the difference between the two numbers is found to be within a certain limit, the circuit element is deemed acceptable, and steps are then taken to test other circuit elements of the printed circuit. If the measured value is found to be higher than the ideal value, the circuit element is deemed to be connected to another circuit element, and a short circuit is determined to be present. If the measured value is found to be lower than the ideal value, the circuit element is deemed to include an open circuit.
Such capacitance testing is primarily performed by measuring how much copper (surface area) is present for each circuit element being tested. All of tee circuit elements present on a particular printed circuit are tested sequentially. Each measured value is compared, in turn, to the corresponding ideal value for that circuit element (previously established) to determine it there are failures, and which of the circuit elements are defective.
Although such testing methods are generally satisfactory, it has been found that the results can be less than satisfactory in situations where circuit elements of the printed circuit being tested differ, even slightly, from the "ideal" printed circuit. These situations can include circuit elements which would be satisfactory in terms of their electrical characteristics, and which would operate acceptably in practice but which, due to over-etching or under-etching during manufacture of the printed circuit, produce a capacitance measurement (i.e., a capacitive signature) which is slightly higher for under-etched parts and slightly lower for over-etched parts. Moreover, the repeatability of line widths will vary from job-to-job, causing still other problems during the testing procedure. Such part-to-part differences can become even more troublesome as the line geometries (i.e., dimensions) shrink.
As an example, in testing circuit elements which would typically exhibit a capacitance of less than 3 pf, such as in chip carriers and the like, tolerances on the order of .+-.20% are used as the threshold for identifying defects present on the printed circuit. At these levels, differences in line width resulting from the initial manufacture of the printed circuit will be very significant. Such differences in line width can cause the test to fail an otherwise acceptable (good) part, and can also cause downtime of the testing apparatus until it can be determined whether the problem is the result of the manufacturing process or the testing apparatus.
Efforts have been made to address this problem. For example, it has been suggested ("Lead Frame Measurement Technique", IBM.RTM. Technical Disclosure Bulletin, Vol. 39, No. 09, September, 1996) to make capacitance measurements relative to each of a series of pin connections associated with a printed circuit, and to compare ratios of the measurements made at the several pins with pre-defined norms. U.S. Pat. No. 5,391,993 suggests averaging adjacent measurements to compensate for irregularities present on a particular part. Others have suggested various measures for adjusting the calculated "ideal" value against which subsequent comparisons are made, including adjustments made to the "tolerance window" which surrounds the ideal value. In practice, however, such efforts have not proven to be entirely satisfactory.
Therefore, the primary object of the present invention is to provide a more accurate way to measure capacitance values for purposes of testing the circuit elements of a printed circuit, or similar part. Another object of the present invention is to adjust for variations in the parts being tested, during the course of the capacitance-testing procedure, to compensate for process variations such as plating height, plating width, etch dissimilarities, dielectric variations, and relative humidity.